LDPC (low density parity check) coded modulation symbol decoding

ABSTRACT

LDPC (Low Density Parity Check) coded modulation symbol decoding. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. The iterative decoding processing may involve updating the check nodes as well as estimating the symbol sequence and updating the symbol nodes. In some embodiments, an alternative hybrid decoding approach may be performed such that a combination of bit level and symbol level decoding is performed. This LDPC symbol decoding out-performs bit decoding only. In addition, it provides comparable or better performance of bit decoding involving iterative updating of the associated metrics.

CROSS REFERENCE TO RELATED PATENTS/PATENT APPLICATIONS ContinuationPriority Claim, 35 U.S.C. §120

The present U.S. Utility Patent Application claims priority pursuant to35 U.S.C. §120, as a continuation, to the following U.S. Utility PatentApplication which is hereby incorporated herein by reference in itsentirety and made part of the present U.S. Utility Patent Applicationfor all purposes:

1. U.S. Utility application Ser. No. 10/668,526, entitled “LDPC (LowDensity Parity Check) coded modulation symbol decoding,” filed Sep. 23,2003, now U.S. Pat. No. 7,159,170 which claims priority pursuant to 35U.S.C. §119(e) to the following U.S. Provisional Patent Applicationswhich are hereby incorporated herein by reference in their entirety andmade part of the present U.S. Utility Patent Application for allpurposes:

-   -   1. U.S. Provisional Application Ser. No. 60/478,690, “Coded        modulation with LDPC (Low Density Parity Check) code using        variable maps and metric updating,” filed Jun. 13, 2003.    -   2. U.S. Provisional Application Ser. No. 60/490,967, “LDPC (Low        Density Parity Check) coded modulation symbol decoding,” filed        Jul. 29, 2003.

Incorporation by Reference

The following U.S. Utility Patent Application is hereby incorporatedherein by reference in its entirety and made part of the present U.S.Utility Patent Application for all purposes:

1. U.S. Utility application Ser. No. 10/264,486, entitled “Variable coderate and signal constellation turbo trellis coded modulation codec,”filed Oct. 4, 2002, now U.S. Pat. No. 7,093,187 B2, issued on Aug. 15,2006, which claims priority pursuant to 35 U.S.C. §119(e) to U.S.Provisional Patent Application Ser. No. 60/384,698, entitled “Variablecode rate and signal constellation turbo trellis coded modulationcodec,” filed May 31, 2002, which also is hereby incorporated herein byreference in its entirety and made part of the present U.S. UtilityPatent Application for all purposes.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

The invention relates generally to communication systems; and, moreparticularly, it relates to decoding of signals within suchcommunication systems.

2. Description of Related Art

Data communication systems have been under continual development formany years. One such type of communication system that has been ofsignificant interest lately is a communication system that employs turbocodes. Another type of communication system that has also receivedinterest is a communication system that employs LDPC (Low Density ParityCheck) coded modulation. A primary directive in these areas ofdevelopment has been to try continually to lower the error floor withina communication system. The ideal goal has been to try to reachShannon's limit in a communication channel. Shannon's limit may beviewed as being the data rate to be used in a communication channel,having a particular SNR (Signal to Noise Ratio), that achieves errorfree transmission through the communication channel. In other words, theShannon limit is the theoretical bound for channel capacity for a givenmodulation and code rate.

LDPC code has been shown to provide for excellent decoding performancethat can approach the Shannon limit in some cases. For example, someLDPC decoders have been shown to come within 0.3 dB (decibels) from thetheoretical Shannon limit. While this example was achieved using anirregular LDPC code of a length of one million, it neverthelessdemonstrates the very promising application of LDPC codes withincommunication systems.

Typical decoding of LDPC coded modulation signals is performed based ona bipartite graph of a given LDPC code such that the graph includes bitnodes and check nodes. The I,Q (In-phase, Quadrature) values associatedwith received symbols are associated with a symbol node, and that symbolnode is associated with corresponding bit nodes. Bit metrics are thencalculated for the individual bits of the corresponding symbols, andthose bit metrics are provided to the bit nodes of the bipartite graphof the given LDPC code. Edge information corresponding to the edges thatinterconnect the bit nodes and the check nodes is calculated, andappropriately updated, and communicated back and forth between the bitnodes and the check nodes during iterative decoding of the LDPC codedsignal. Therefore, such LDPC decoding is typically performed withrespect to the bit nodes and the check nodes of the LDPC bipartitegraph. One disadvantage of this approach to LDPC decoding is that it canbe very memory and processing resource consumptive. Even in instanceswhere there are sufficient memory and processing resources available,the previous approaches to perform LDPC decoding typically do not give asufficiently high level of performance for some applications. With theever-improvements developments in memory management and processingresource allocation, a higher performance means by which LDPC codedmodulation signals may be decoded would be desirable.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to apparatus and methods of operationthat are further described in the following Brief Description of theSeveral Views of the Drawings, the Detailed Description of theInvention, and the claims. Other features and advantages of the presentinvention will become apparent from the following detailed descriptionof the invention made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a system diagram illustrating an embodiment of a satellitecommunication system that is built according to the invention.

FIG. 2 is a system diagram illustrating an embodiment of an HDTV (HighDefinition Television) communication system that is built according tothe invention.

FIG. 3A and FIG. 3B are system diagrams illustrating embodiment ofuni-directional cellular communication systems that are built accordingto the invention.

FIG. 4 is a system diagram illustrating an embodiment of abi-directional cellular communication system that is built according tothe invention.

FIG. 5 is a system diagram illustrating an embodiment of auni-directional microwave communication system that is built accordingto the invention.

FIG. 6 is a system diagram illustrating an embodiment of abi-directional microwave communication system that is built according tothe invention.

FIG. 7 is a system diagram illustrating an embodiment of auni-directional point-to-point radio communication system that is builtaccording to the invention.

FIG. 8 is a system diagram illustrating an embodiment of abi-directional point-to-point radio communication system that is builtaccording to the invention.

FIG. 9 is a system diagram illustrating an embodiment of auni-directional communication system that is built according to theinvention.

FIG. 10 is a system diagram illustrating an embodiment of abi-directional communication system that is built according to theinvention.

FIG. 11 is a system diagram illustrating an embodiment of a one to manycommunication system that is built according to the invention.

FIG. 12 is a diagram illustrating an embodiment of a WLAN (WirelessLocal Area Network) that may be implemented according to the invention.

FIG. 13 is a diagram illustrating an embodiment of a DSL (DigitalSubscriber Line) communication system that may be implemented accordingto the invention.

FIG. 14 is a system diagram illustrating an embodiment of a fiber-opticcommunication system that is built according to the invention.

FIG. 15 is a system diagram illustrating an embodiment of a satellitereceiver STB (Set Top Box) system that is built according to theinvention.

FIG. 16 is a diagram illustrating an embodiment of an LDPC (Low DensityParity Check) code bipartite graph.

FIG. 17A is a diagram illustrating an embodiment of direct combining ofLDPC (Low Density Parity Check) coding and modulation encoding.

FIG. 17B is a diagram illustrating an embodiment of BICM (BitInterleaved Coded Modulation) that is employed in conjunction with LDPC(Low Density Parity Check) coding and modulation encoding.

FIG. 17C is a diagram illustrating an embodiment of multilevel codedmodulation encoding.

FIG. 18 is a diagram illustrating an embodiment of a variable signalmapping LDPC (Low Density Parity Check) coded modulation system that isbuilt in accordance with invention.

FIG. 19 is a diagram illustrating an embodiment of LDPC (Low DensityParity Check) coded modulation decoding functionality using bit metricaccording to the invention.

FIG. 20 is a diagram illustrating an alternative embodiment of LDPCcoded modulation decoding functionality using bit metric according tothe invention (when performing n number of iterations).

FIG. 21 is a diagram illustrating an alternative embodiment of LDPC (LowDensity Parity Check) coded modulation decoding functionality using bitmetric (with bit metric updating) according to the invention.

FIG. 22 is a diagram illustrating an alternative embodiment of LDPCcoded modulation decoding functionality using bit metric (with bitmetric updating) according to the invention (when performing n number ofiterations).

FIG. 23A is a diagram illustrating bit decoding using bit metric (shownwith respect to an LDPC (Low Density Parity Check) code bipartite graph)according to the invention.

FIG. 23B is a diagram illustrating bit decoding using bit metricupdating (shown with respect to an LDPC (Low Density Parity Check) codebipartite graph) according to the invention.

FIG. 24A is a diagram illustrating an LDPC (Low Density Parity Check)coded modulation tripartite graph with symbol nodes connected to bitnodes according to the invention.

FIG. 24B is a diagram illustrating an LDPC (Low Density Parity Check)coded modulation bipartite graph with symbol nodes connected directly tocheck nodes according to the invention (this bipartite graph isgenerated from the tripartite graph shown in FIG. 24A).

FIG. 25A is a diagram illustrating symbol decoding (shown with respectto an LDPC (Low Density Parity Check) coded modulation bipartite graph)according to the invention.

FIG. 25B is a diagram illustrating an embodiment of symbol decodingfunctionality (supported with an LDPC (Low Density Parity Check) codedmodulation bipartite graph) according to the invention.

FIG. 26 is a diagram illustrating an embodiment of performancecomparison of symbol vs. bit decoding of LDPC (Low Density Parity Check)code modulation signals according to the invention.

FIG. 27 is a diagram illustrating an embodiment of hybrid decodingfunctionality that reduces the complexity of symbol decoding of LDPCcoded modulation signals according to the invention.

FIG. 28A is a flowchart illustrating an embodiment of a method forsymbol decoding of LDPC coded modulation signals according to theinvention.

FIG. 28B is a flowchart illustrating an embodiment of a hybrid decodingmethod of LDPC coded modulation signals according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

Various aspects of the invention may be found in any number of devicesthat perform symbol decoding of LDPC (Low Density Parity Check) codedsignals. In some instances, the LDPC symbol decoding is performed onsignals whose code rate and/or modulation may vary as frequently as on asymbol by symbol basis.

Various system embodiments are described below where any of the variousaspects of the invention may be implemented. In general, any device thatperforms symbol decoding of LDPC coded signals may benefit from theinvention.

FIG. 1 is a system diagram illustrating an embodiment of a satellitecommunication system that is built according to the invention. Asatellite transmitter is communicatively coupled to a satellite dishthat is operable to communicate with a satellite. The satellitetransmitter may also be communicatively coupled to a wired network. Thiswired network may include any number of networks including the Internet,proprietary networks, other wired networks and/or WANs (Wide AreaNetworks). The satellite transmitter employs the satellite dish tocommunicate to the satellite via a wireless communication channel. Thesatellite is able to communicate with one or more satellite receivers(each having a satellite dish). Each of the satellite receivers may alsobe communicatively coupled to a display.

Here, the communication to and from the satellite may cooperatively beviewed as being a wireless communication channel, or each of thecommunication links to and from the satellite may be viewed as being twodistinct wireless communication channels.

For example, the wireless communication “channel” may be viewed as notincluding multiple wireless hops in one embodiment. In other multi-hopembodiments, the satellite receives a signal received from the satellitetransmitter (via its satellite dish), amplifies it, and relays it tosatellite receiver (via its satellite dish); the satellite receiver mayalso be implemented using terrestrial receivers such as satellitereceivers, satellite based telephones, and/or satellite based Internetreceivers, among other receiver types. In the case where the satellitereceives a signal received from the satellite transmitter (via itssatellite dish), amplifies it, and relays it, the satellite may beviewed as being a “transponder;” this is a multi-hop embodiment. Inaddition, other satellites may exist that perform both receiver andtransmitter operations in cooperation with the satellite. In this case,each leg of an up-down transmission via the wireless communicationchannel would be considered separately.

In whichever embodiment, the satellite communicates with the satellitereceiver. The satellite receiver may be viewed as being a mobile unit incertain embodiments (employing a local antenna); alternatively, thesatellite receiver may be viewed as being a satellite earth station thatmay be communicatively coupled to a wired network in a similar manner inwhich the satellite transmitter may also be communicatively coupled to awired network.

The satellite transmitter is operable to encode information (using anencoder) that is to be transmitted to the satellite receiver; thesatellite receiver is operable to decode the transmitted signal (using adecoder). The encoder may be implemented to perform encoding using LDPCcoded modulation, and the LDPC encoding may be performed to generate anLDPC coded signal whose code rate and/or modulation (constellation andmapping) may vary as frequently as on a symbol by symbol basis. Thedecoders within the satellite receivers may be implemented to performdecoding of LDPC coded signals. This LDPC decoding may be implemented toperform symbol decoding within the iterative decoding processing. Inaddition, this LDPC decoding may also be implemented to accommodatedecoding processing of an LDPC coded signal whose code rate and/ormodulation (constellation and mapping) may vary as frequently as on asymbol by symbol basis. This diagram shows just one of the manyembodiments where one or more of the various aspects of the inventionmay be found.

FIG. 2 is a system diagram illustrating an embodiment of an HDTV (HighDefinition Television) communication system that is built according tothe invention. An HDTV transmitter is communicatively coupled to atower. The HDTV transmitter, using its tower, transmits a signal to alocal tower dish via a wireless communication channel. The local towerdish may communicatively couple to an HDTV STB (Set Top Box) receivervia a coaxial cable. The HDTV STB receiver includes the functionality toreceive the wireless transmitted signal that has been received by thelocal tower dish. This functionality may include any transformationand/or down-converting that may be needed to accommodate anyup-converting that may have been performed before and duringtransmission of the signal from the HDTV transmitter and itscorresponding tower to transform the signal into a format that iscompatible with the communication channel across which it istransmitted.

The HDTV STB receiver is also communicatively coupled to an HDTV displaythat is able to display the demodulated and decoded wireless transmittedsignals received by the HDTV STB receiver and its local tower dish. TheHDTV transmitter (via its tower) transmits a signal directly to thelocal tower dish via the wireless communication channel in thisembodiment. In alternative embodiments, the HDTV transmitter may firstreceive a signal from a satellite, using a satellite earth station thatis communicatively coupled to the HDTV transmitter, and then transmitthis received signal to the local tower dish via the wirelesscommunication channel. In this situation, the HDTV transmitter operatesas a relaying element to transfer a signal originally provided by thesatellite that is destined for the HDTV STB receiver. For example,another satellite earth station may first transmit a signal to thesatellite from another location, and the satellite may relay this signalto the satellite earth station that is communicatively coupled to theHDTV transmitter. The HDTV transmitter performs receiver functionalityand then transmits its received signal to the local tower dish.

In even other embodiments, the HDTV transmitter employs its satelliteearth station to communicate to the satellite via a wirelesscommunication channel. The satellite is able to communicate with a localsatellite dish; the local satellite dish communicatively couples to theHDTV STB receiver via a coaxial cable. This path of transmission showsyet another communication path where the HDTV STB receiver maycommunicate with the HDTV transmitter.

In whichever embodiment and whichever signal path the HDTV transmitteremploys to communicate with the HDTV STB receiver, the HDTV STB receiveris operable to receive communication transmissions from the HDTVtransmitter.

The HDTV transmitter is operable to encode information (using anencoder) that is to be transmitted to the HDTV STB receiver; the HDTVSTB receiver is operable to decode the transmitted signal (using adecoder).

As within other embodiments that employ an encoder and a decoder, theencoder may be implemented to perform encoding using LDPC codedmodulation, and the LDPC encoding may be performed to generate an LDPCcoded signal whose code rate and/or modulation (constellation andmapping) may vary as frequently as on a symbol by symbol basis. Thedecoder may be implemented to perform decoding of LDPC coded signals.This LDPC decoding may be implemented to perform symbol decoding withinthe iterative decoding processing. In addition, this LDPC decoding mayalso be implemented to accommodate decoding processing of an LDPC codedsignal whose code rate and/or modulation (constellation and mapping) mayvary as frequently as on a symbol by symbol basis. This diagram showsyet another embodiment where one or more of the various aspects of theinvention may be found.

FIG. 3A and FIG. 3B are system diagrams illustrating embodiments ofuni-directional cellular communication systems that are built accordingto the invention.

Referring to the FIG. 3A, a mobile transmitter includes a local antennacommunicatively coupled thereto. The mobile transmitter may be anynumber of types of transmitters including a one way cellular telephone,a wireless pager unit, a mobile computer having transmit functionality,or any other type of mobile transmitter. The mobile transmittertransmits a signal, using its local antenna, to a cellular tower via awireless communication channel. The cellular tower is communicativelycoupled to a base station receiver; the receiving tower is operable toreceive data transmission from the local antenna of the mobiletransmitter that has been communicated via the wireless communicationchannel. The cellular tower communicatively couples the received signalto the base station receiver.

The mobile transmitter is operable to encode information (using anencoder) that is to be transmitted to the base station receiver; thebase station receiver is operable to decode the transmitted signal(using a decoder).

As within other embodiments that employ an encoder and a decoder, theencoder may be implemented to perform encoding using LDPC codedmodulation, and the LDPC encoding may be performed to generate an LDPCcoded signal whose code rate and/or modulation (constellation andmapping) may vary as frequently as on a symbol by symbol basis. Thedecoder may be implemented to perform decoding of LDPC coded signals.This LDPC decoding may be implemented to perform symbol decoding withinthe iterative decoding processing. In addition, this LDPC decoding mayalso be implemented to accommodate decoding processing of an LDPC codedsignal whose code rate and/or modulation (constellation and mapping) mayvary as frequently as on a symbol by symbol basis. This diagram showsyet another embodiment where one or more of the various aspects of theinvention may be found.

Referring to the FIG. 3B, a base station transmitter includes a cellulartower communicatively coupled thereto. The base station transmitter,using its cellular tower, transmits a signal to a mobile receiver via acommunication channel. The mobile receiver may be any number of types ofreceivers including a one-way cellular telephone, a wireless pager unit,a mobile computer having receiver functionality, or any other type ofmobile receiver. The mobile receiver is communicatively coupled to alocal antenna; the local antenna is operable to receive datatransmission from the cellular tower of the base station transmitterthat has been communicated via the wireless communication channel. Thelocal antenna communicatively couples the received signal to the mobilereceiver.

The base station transmitter is operable to encode information (using anencoder) that is to be transmitted to the mobile receiver; the mobilereceiver is operable to decode the transmitted signal (using a decoder).

As within other embodiments that employ an encoder and a decoder, theencoder may be implemented to perform encoding using LDPC codedmodulation, and the LDPC encoding may be performed to generate an LDPCcoded signal whose code rate and/or modulation (constellation andmapping) may vary as frequently as on a symbol by symbol basis. Thedecoder may be implemented to perform decoding of LDPC coded signals.This LDPC decoding may be implemented to perform symbol decoding withinthe iterative decoding processing. In addition, this LDPC decoding mayalso be implemented to accommodate decoding processing of an LDPC codedsignal whose code rate and/or modulation (constellation and mapping) mayvary as frequently as on a symbol by symbol basis. This diagram showsyet another embodiment where one or more of the various aspects of theinvention may be found.

FIG. 4 is a system diagram illustrating an embodiment of abi-directional cellular communication system, built according to theinvention, where the communication can go to and from the base stationtransceiver and to and from the mobile transceiver via the wirelesscommunication channel.

Referring to the FIG. 4, a base station transceiver includes a cellulartower communicatively coupled thereto. The base station transceiver,using its cellular tower, transmits a signal to a mobile transceiver viaa communication channel. The reverse communication operation may also beperformed. The mobile transceiver is able to transmit a signal to thebase station transceiver as well. The mobile transceiver may be anynumber of types of transceiver including a cellular telephone, awireless pager unit, a mobile computer having transceiver functionality,or any other type of mobile transceiver. The mobile transceiver iscommunicatively coupled to a local antenna; the local antenna isoperable to receive data transmission from the cellular tower of thebase station transceiver that has been communicated via the wirelesscommunication channel. The local antenna communicatively couples thereceived signal to the mobile transceiver.

The base station transceiver is operable to encode information (usingits corresponding encoder) that is to be transmitted to the mobiletransceiver; the mobile transceiver is operable to decode thetransmitted signal (using its corresponding decoder). Similarly, mobiletransceiver is operable to encode information (using its correspondingencoder) that is to be transmitted to the base station transceiver; thebase station transceiver is operable to decode the transmitted signal(using its corresponding decoder).

As within other embodiments that employ an encoder and a decoder, theencoder of either of the base station transceiver or the mobiletransceiver may be implemented to perform encoding using LDPC codedmodulation, and the LDPC encoding may be performed to generate an LDPCcoded signal whose code rate and/or modulation (constellation andmapping) may vary as frequently as on a symbol by symbol basis. Thedecoder of either of the base station transceiver or the mobiletransceiver may be implemented to perform decoding of LDPC codedsignals. This LDPC decoding may be implemented to perform symboldecoding within the iterative decoding processing. In addition, thisLDPC decoding may also be implemented to accommodate decoding processingof an LDPC coded signal whose code rate and/or modulation (constellationand mapping) may vary as frequently as on a symbol by symbol basis. Thisdiagram shows yet another embodiment where one or more of the variousaspects of the invention may be found.

FIG. 5 is a system diagram illustrating an embodiment of auni-directional microwave communication system that is built accordingto the invention. A microwave transmitter is communicatively coupled toa microwave tower. The microwave transmitter, using its microwave tower,transmits a signal to a microwave tower via a wireless communicationchannel. A microwave receiver is communicatively coupled to themicrowave tower. The microwave tower is able to receive transmissionsfrom the microwave tower that have been communicated via the wirelesscommunication channel.

The microwave transmitter is operable to encode information (using anencoder) that is to be transmitted to the microwave receiver; themicrowave receiver is operable to decode the transmitted signal (using adecoder).

As within other embodiments that employ an encoder and a decoder, theencoder may be implemented to perform encoding using LDPC codedmodulation, and the LDPC encoding may be performed to generate an LDPCcoded signal whose code rate and/or modulation (constellation andmapping) may vary as frequently as on a symbol by symbol basis. Thedecoder may be implemented to perform decoding of LDPC coded signals.This LDPC decoding may be implemented to perform symbol decoding withinthe iterative decoding processing. In addition, this LDPC decoding mayalso be implemented to accommodate decoding processing of an LDPC codedsignal whose code rate and/or modulation (constellation and mapping) mayvary as frequently as on a symbol by symbol basis. This diagram showsyet another embodiment where one or more of the various aspects of theinvention may be found.

FIG. 6 is a system diagram illustrating an embodiment of abi-directional microwave communication system that is built according tothe invention. Within the FIG. 6, a first microwave transceiver iscommunicatively coupled to a first microwave tower. The first microwavetransceiver, using the first microwave tower (the first microwavetransceiver's microwave tower), transmits a signal to a second microwavetower of a second microwave transceiver via a wireless communicationchannel. The second microwave transceiver is communicatively coupled tothe second microwave tower (the second microwave transceiver's microwavetower). The second microwave tower is able to receive transmissions fromthe first microwave tower that have been communicated via the wirelesscommunication channel. The reverse communication operation may also beperformed using the first and second microwave transceivers.

Each of the microwave transceivers is operable to encode information(using an encoder) that is to be transmitted to the other microwavetransceiver; each microwave transceiver is operable to decode thetransmitted signal (using a decoder) that it receives. Each of themicrowave transceivers includes an encoder and a decoder.

As within other embodiments that employ an encoder and a decoder, theencoder of either of the microwave transceivers may be implemented toperform encoding using LDPC coded modulation, and the LDPC encoding maybe performed to generate an LDPC coded signal whose code rate and/ormodulation (constellation and mapping) may vary as frequently as on asymbol by symbol basis. The decoder of either of the microwavetransceivers may be implemented to perform decoding of LDPC codedsignals. This LDPC decoding may be implemented to perform symboldecoding within the iterative decoding processing. In addition, thisLDPC decoding may also be implemented to accommodate decoding processingof an LDPC coded signal whose code rate and/or modulation (constellationand mapping) may vary as frequently as on a symbol by symbol basis. Thisdiagram shows yet another embodiment where one or more of the variousaspects of the invention may be found.

FIG. 7 is a system diagram illustrating an embodiment of aunidirectional point-to-point radio communication system, builtaccording to the invention, where the communication goes from a mobileunit transmitter to a mobile unit receiver via the wirelesscommunication channel.

A mobile unit transmitter includes a local antenna communicativelycoupled thereto. The mobile unit transmitter, using its local antenna,transmits a signal to a local antenna of a mobile unit receiver via awireless communication channel.

The mobile unit transmitter is operable to encode information (using anencoder) that is to be transmitted to the mobile unit receiver; themobile unit receiver is operable to decode the transmitted signal (usinga decoder).

As within other embodiments that employ an encoder and a decoder, theencoder may be implemented to perform encoding using LDPC codedmodulation, and the LDPC encoding may be performed to generate an LDPCcoded signal whose code rate and/or modulation (constellation andmapping) may vary as frequently as on a symbol by symbol basis. Thedecoder may be implemented to perform decoding of LDPC coded signals.This LDPC decoding may be implemented to perform symbol decoding withinthe iterative decoding processing. In addition, this LDPC decoding mayalso be implemented to accommodate decoding processing of an LDPC codedsignal whose code rate and/or modulation (constellation and mapping) mayvary as frequently as on a symbol by symbol basis. This diagram showsyet another embodiment where one or more of the various aspects of theinvention may be found.

FIG. 8 is a system diagram illustrating an embodiment of abi-directional point-to-point radio communication system that is builtaccording to the invention. A first mobile unit transceiver iscommunicatively coupled to a first local antenna. The first mobile unittransceiver, using the first local antenna (the first mobile unittransceiver's local antenna), transmits a signal to a second localantenna of a second mobile unit transceiver via a wireless communicationchannel. The second mobile unit transceiver is communicatively coupledto the second local antenna (the second mobile unit transceiver's localantenna). The second local antenna is able to receive transmissions fromthe first local antenna that have been communicated via thecommunication channel. The reverse communication operation may also beperformed using the first and second mobile unit transceivers.

Each mobile unit transceiver is operable to encode information (usingits corresponding encoder) that is to be transmitted to the other mobileunit transceiver; each mobile unit transceiver is operable to decode thetransmitted signal (using its corresponding decoder) that it receives.

As within other embodiments that employ an encoder and a decoder, theencoder of either of the mobile unit transceivers may be implemented toperform encoding using LDPC coded modulation, and the LDPC encoding maybe performed to generate an LDPC coded signal whose code rate and/ormodulation (constellation and mapping) may vary as frequently as on asymbol by symbol basis. The decoder of either of the mobile unittransceivers may be implemented to perform decoding of LDPC codedsignals. This LDPC decoding may be implemented to perform symboldecoding within the iterative decoding processing. In addition, thisLDPC decoding may also be implemented to accommodate decoding processingof an LDPC coded signal whose code rate and/or modulation (constellationand mapping) may vary as frequently as on a symbol by symbol basis. Thisdiagram shows yet another embodiment where one or more of the variousaspects of the invention may be found.

FIG. 9 is a system diagram illustrating an embodiment of auni-directional communication system that is built according to theinvention. A transmitter communicates to a receiver via auni-directional communication channel. The uni-directional communicationchannel may be a wireline (or wired) communication channel or a wirelesscommunication channel without departing from the scope and spirit of theinvention. The wired media by which the uni-directional communicationchannel may be implemented are varied, including coaxial cable,fiber-optic cabling, and copper cabling, among other types of “wiring.”Similarly, the wireless manners in which the uni-directionalcommunication channel may be implemented are varied, including satellitecommunication, cellular communication, microwave communication, andradio communication, among other types of wireless communication.

The transmitter is operable to encode information (using an encoder)that is to be transmitted to the receiver; the receiver is operable todecode the transmitted signal (using a decoder).

As within other embodiments that employ an encoder and a decoder, theencoder may be implemented to perform encoding using LDPC codedmodulation, and the LDPC encoding may be performed to generate an LDPCcoded signal whose code rate and/or modulation (constellation andmapping) may vary as frequently as on a symbol by symbol basis. Thedecoder may be implemented to perform decoding of LDPC coded signals.This LDPC decoding may be implemented to perform symbol decoding withinthe iterative decoding processing. In addition, this LDPC decoding mayalso be implemented to accommodate decoding processing of an LDPC codedsignal whose code rate and/or modulation (constellation and mapping) mayvary as frequently as on a symbol by symbol basis. This diagram showsyet another embodiment where one or more of the various aspects of theinvention may be found.

FIG. 10 is a system diagram illustrating an embodiment of abi-directional communication system that is built according to theinvention. A first transceiver is communicatively coupled to a secondtransceiver via a bi-directional communication channel. Thebi-directional communication channel may be a wireline (or wired)communication channel or a wireless communication channel withoutdeparting from the scope and spirit of the invention. The wired media bywhich the bi-directional communication channel may be implemented arevaried, including coaxial cable, fiber-optic cabling, and coppercabling, among other types of “wiring.” Similarly, the wireless mannersin which the bi-directional communication channel may be implemented arevaried, including satellite communication, cellular communication,microwave communication, and radio communication, among other types ofwireless communication.

Each of the transceivers is operable to encode information (using itscorresponding encoder) that is to be transmitted to the othertransceiver; each transceiver is operable to decode the transmittedsignal (using its corresponding decoder) that it receives.

As within other embodiments that employ an encoder and a decoder, theencoder of either of the transceivers may be implemented to performencoding using LDPC coded modulation, and the LDPC encoding may beperformed to generate an LDPC coded signal whose code rate and/ormodulation (constellation and mapping) may vary as frequently as on asymbol by symbol basis. The decoder of either of the transceivers may beimplemented to perform decoding of LDPC coded signals. This LDPCdecoding may be implemented to perform symbol decoding within theiterative decoding processing. In addition, this LDPC decoding may alsobe implemented to accommodate decoding processing of an LDPC codedsignal whose code rate and/or modulation (constellation and mapping) mayvary as frequently as on a symbol by symbol basis. This diagram showsyet another embodiment where one or more of the various aspects of theinvention may be found.

FIG. 11 is a system diagram illustrating an embodiment of a one to manycommunication system that is built according to the invention. Atransmitter is able to communicate, via broadcast in certainembodiments, with a number of receivers, shown as receivers 1, . . . , nvia a uni-directional communication channel. The uni-directionalcommunication channel may be a wireline (or wired) communication channelor a wireless communication channel without departing from the scope andspirit of the invention. The wired media by which the bi-directionalcommunication channel may be implemented are varied, including coaxialcable, fiber-optic cabling, and copper cabling, among other types of“wiring.” Similarly, the wireless manners in which the bi-directionalcommunication channel may be implemented are varied, including satellitecommunication, cellular communication, microwave communication, andradio communication, among other types of wireless communication.

A distribution point is employed within the one to many communicationsystem to provide the appropriate communication to the receivers 1, . .. , and n. In certain embodiments, the receivers 1, . . . , and n eachreceive the same communication and individually discern which portion ofthe total communication is intended for them.

The transmitter is operable to encode information (using an encoder)that is to be transmitted to the receivers 1, . . . , and n; each of thereceivers 1, . . . , and n is operable to decode the transmitted signal(using a decoder).

As within other embodiments that employ an encoder and a decoder, theencoder may be implemented to perform encoding using LDPC codedmodulation, and the LDPC encoding may be performed to generate an LDPCcoded signal whose code rate and/or modulation (constellation andmapping) may vary as frequently as on a symbol by symbol basis. Thedecoders of any of the receivers 1, . . . , and n may be implemented toperform decoding of LDPC coded signals. This LDPC decoding may beimplemented to perform symbol decoding within the iterative decodingprocessing. In addition, this LDPC decoding may also be implemented toaccommodate decoding processing of an LDPC coded signal whose code rateand/or modulation (constellation and mapping) may vary as frequently ason a symbol by symbol basis. This diagram shows yet another embodimentwhere one or more of the various aspects of the invention may be found.

FIG. 12 is a diagram illustrating an embodiment of a WLAN (WirelessLocal Area Network) that may be implemented according to the invention.The WLAN communication system may be implemented to include a number ofdevices that are all operable to communicate with one another via theWLAN. For example, the various devices that each include thefunctionality to interface with the WLAN may include any 1 or more of alaptop computer, a television, a PC (Personal Computer), a pen computer(that may be viewed as being a PDA (Personal Digital Assistant) in someinstances, a personal electronic planner, or similar device), a mobileunit (that may be viewed as being a telephone, a pager, or some othermobile WLAN operable device), and/or a stationary unit (that may beviewed as a device that typically resides in a single location withinthe WLAN). The antennae of the various WLAN interactive devices may beintegrated into the corresponding devices without departing from thescope and spirit of the invention as well.

This illustrated group of devices that may interact with the WLAN is notintended to be an exhaustive list of device that may interact with aWLAN, and a generic device shown as a WLAN interactive device representsa generic device that includes the functionality in order to interactivewith the WLAN itself and/or the other devices that are associated withthe WLAN. Any one of these devices that associate with the WLAN may beviewed generically as being a WLAN interactive device without departingfrom the scope and spirit of the invention. Each of the devices and theWLAN interactive device may be viewed as being located at nodes of theWLAN.

It is also noted that the WLAN itself may also include functionality toallow interfacing with other networks as well. These external networksmay generically be referred to as WANs (Wide Area Networks). Forexample, the WLAN may include an Internet I/F (interface) that allowsfor interfacing to the Internet itself. This Internet I/F may be viewedas being a base station device for the WLAN that allows any one of theWLAN interactive devices to access the Internet.

It is also noted that the WLAN may also include functionality to allowinterfacing with other networks (e.g., other WANs) besides simply theInternet. For example, the WLAN may include a microwave tower I/F thatallows for interfacing to a microwave tower thereby allowingcommunication with one or more microwave networks. Similar to theInternet I/F described above, the microwave tower I/F may be viewed asbeing a base station device for the WLAN that allows any one of the WLANinteractive devices to access the one or more microwave networks via themicrowave tower.

Moreover, the WLAN may include a satellite earth station I/F that allowsfor interfacing to a satellite earth station thereby allowingcommunication with one or more satellite networks. The satellite earthstation I/F may be viewed as being a base station device for the WLANthat allows any one of the WLAN interactive devices to access the one ormore satellite networks via the satellite earth station I/F.

This finite listing of various network types that may interface to theWLAN is also not intended to be exhaustive. For example, any othernetwork may communicatively couple to the WLAN via an appropriate I/Fthat includes the functionality for any one of the WLAN interactivedevices to access the other network.

Any of the various WLAN interactive devices described within thisembodiment may include an encoder and a decoder to allow bidirectionalcommunication with the other WLAN interactive device and/or the WANs.

Again, as within other embodiments that employ an encoder and a decoder,any of the encoder of within the various devices may be implemented toperform encoding using LDPC coded modulation, and the LDPC encoding maybe performed to generate an LDPC coded signal whose code rate and/ormodulation (constellation and mapping) may vary as frequently as on asymbol by symbol basis. The decoders of any of the various devices maybe implemented to perform decoding of LDPC coded signals. This LDPCdecoding may be implemented to perform symbol decoding within theiterative decoding processing. In addition, this LDPC decoding may alsobe implemented to accommodate decoding processing of an LDPC codedsignal whose code rate and/or modulation (constellation and mapping) mayvary as frequently as on a symbol by symbol basis. This diagram showsyet another embodiment where one or more of the various aspects of theinvention may be found.

In general, any one of the WLAN interactive devices may be characterizedas being an IEEE (Institute of Electrical & Electronics Engineers)802.11 operable device. For example, such an 802.11 operable device maybe an 802.11a operable device, an 802.11b operable device, or an 802.11goperable device. The IEEE 802.11g specification extends the rates forpacket transmission in the 2.4 GHz frequency band. This is achieved byallowing packets, also known as frames, of two distinct types to coexistin this band. Frames utilizing DSSS/CCK (Direct Sequence Spread Spectrumwith Complementary Code Keying) have been specified for transmission inthe 2.4 GHz band at rates up to 11 Mbps (Mega-bits per second) as partof the 802.11b standard. The 802.11a standard uses a different frameformat with OFDM (Orthogonal Frequency Division Multiplexing) totransmit at rates up to 54 Mbps with carrier frequencies in the 5 GHzrange. The 802.11g specification allows for such OFDM frames to coexistwith DSSS/CCK frames at 2.4 GHz.

FIG. 13 is a diagram illustrating an embodiment of a DSL (DigitalSubscriber Line) communication system that may be implemented accordingto the invention. The DSL communication system includes an interfacingto the Internet (or some other WAN). In this diagram, the Internetitself is shown, but other WANs may also be employed without departingfrom the scope and spirit of the invention. An ISP (Internet ServiceProvider) is operable to communicate data to and from the Internet. TheISP communicatively couples to a CO (Central Office) that is typicallyoperated by a telephones service company. The CO may also allow providetelephone services to one or more subscribers. However, the CO may alsobe implemented to allow interfacing of Internet traffic to and from oneor more users (whose interactive devices are shown as user devices).These user devices may be a wide variety of devices including desk-topcomputers, laptop computers, servers, and/or hand held devices withoutdeparting from the scope and spirit of the invention. Any of these userdevices may be wired or wireless typed devices as well. Each of the userdevices is operably coupled to the CO via a DSL modem. The DSL modem mayalso be communicatively coupled to a multiple user access point or hubto allow more than one user device to access the Internet.

The CO and the various DSL modems may also be implemented to include anencoder and a decoder to allow bi-directional communication therein. Forexample, the CO is operable to encode and decode data when communicatingto and from the various DSL modems and the ISP. Similarly, each of thevarious DSL modems is operable to encode and decode data whencommunicating to and from the CO and its respective one or more userdevices.

Again, as within other embodiments that employ an encoder and a decoder,the encoder of any of the CO and the various DSL modems may beimplemented to perform encoding using LDPC coded modulation, and theLDPC encoding may be performed to generate an LDPC coded signal whosecode rate and/or modulation (constellation and mapping) may vary asfrequently as on a symbol by symbol basis. The decoder of any of the COand the various DSL modem may be implemented to perform decoding of LDPCcoded signals. This LDPC decoding may be implemented to perform symboldecoding within the iterative decoding processing. In addition, thisLDPC decoding may also be implemented to accommodate decoding processingof an LDPC coded signal whose code rate and/or modulation (constellationand mapping) may vary as frequently as on a symbol by symbol basis. Thisdiagram shows yet another embodiment where one or more of the variousaspects of the invention may be found.

FIG. 14 is a system diagram illustrating an embodiment of a fiber-opticcommunication system that is built according to the invention. Thefiber-optic communication system may be implemented to support encodingand/or decoding of LDPC coded signals. In some instances, these LDPCcoded signals include a code rate and/or modulation (constellation andmapping) that may vary as frequently as on a symbol by symbol basis.Moreover, the fiber-optic communication system may be implemented tosupport LDPC symbol decoding within the iterative decoding processing.

The fiber-optic communication system includes a DWDM (Dense WavelengthDivision Multiplexing (within the context of fiber opticcommunications)) line card that is interposed between a line side and aclient side. DWDM is a technology that has gained increasing interestrecently. From both technical and economic perspectives, the ability toprovide potentially unlimited transmission capacity is the most obviousadvantage of DWDM technology. The current investment already made withinfiber-optic infrastructure can not only be preserved when using DWDM,but it may even be optimized by a factor of at least 32. As demandschange, more capacity can be added, either by simple equipment upgradesor by increasing the number of wavelengths (lambdas) on the fiber-opticcabling itself, without expensive upgrades. Capacity can be obtained forthe cost of the equipment, and existing fiber plant investment isretained. From the bandwidth perspective, some of the most compellingtechnical advantage of DWDM can be summarized as follows:

The transparency of DWDM: Because DWDM is a PHY (physical layer)architecture, it can transparently support both TDM (Time DivisionMultiplexing) and data formats such as ATM (Asynchronous Transfer Mode),Gigabit Ethernet, ESCON, and Fibre Channel with open interfaces over acommon physical layer.

The scalability of DWDM: DWDM can leverage the abundance of dark fiberin many metropolitan area and enterprise networks to quickly meet demandfor capacity on point-to-point links and on spans of existing SONET/SDHrings.

The dynamic provisioning capabilities of DWDM: the fast, simple, anddynamic provisioning of network connections give providers the abilityto provide high-bandwidth services in days rather than months.

Fiber-optic interfacing is employed at each of the client and line sidesof the DWDM line card. The DWDM line card includes a transport processorthat includes functionality to support DWDM long haul transport, DWDMmetro transport, next-generation SONET/SDH multiplexers, digitalcross-connects, and fiber-optic terminators and test equipment. On theline side, the DWDM line card includes a transmitter, that is operableto perform electrical to optical conversion for interfacing to anoptical medium, and a receiver, that is operable to perform optical toelectrical conversion for interfacing from the optical medium. On theclient side, the DWDM line card includes a 10G serial module that isoperable to communicate with any other devices on the client side of thefiber-optic communication system using a fiber-optic interface.Alternatively, the interface may be implemented using non-fiber-opticmedia, including copper cabling and/or some other type of interfacemedium.

The DWDM transport processor of the DWDM line card includes a decoderthat is used to decode received signals from either one or both of theline and client sides and an encoder that is used to encode signals tobe transmitted to either one or both of the line and client sides.

As within other embodiments that employ an encoder and a decoder, theencoder may be implemented to perform encoding using LDPC codedmodulation, and the LDPC encoding may be performed to generate an LDPCcoded signal whose code rate and/or modulation (constellation andmapping) may vary as frequently as on a symbol by symbol basis. Thedecoder may be implemented to perform decoding of LDPC coded signals.This LDPC decoding may be implemented to perform symbol decoding withinthe iterative decoding processing. In addition, this LDPC decoding mayalso be implemented to accommodate decoding processing of an LDPC codedsignal whose code rate and/or modulation (constellation and mapping) mayvary as frequently as on a symbol by symbol basis. This diagram showsyet another embodiment where one or more of the various aspects of theinvention may be found.

FIG. 15 is a system diagram illustrating an embodiment of a satellitereceiver STB (Set Top Box) system that is built according to theinvention. The satellite receiver STB system includes an advancedmodulation satellite receiver that is implemented in an all digitalarchitecture. Moreover, the advanced modulation satellite receiver maybe implemented within a single integrated circuit in some embodiments.The satellite receiver STB system includes a satellite tuner thatreceives a signal via the L-band. The satellite tuner extracts I,Q(in-phase and quadrature) components from a signal received from theL-band and provides them to the advanced modulation satellite receiver.The advanced modulation satellite receiver includes a decoder.

As within other embodiments that employ a decoder, the decoder may beimplemented to perform decoding of LDPC coded signals. This LDPCdecoding may be implemented to perform symbol decoding within theiterative decoding processing. In addition, this LDPC decoding may alsobe implemented to accommodate decoding processing of an LDPC codedsignal whose code rate and/or modulation (constellation and mapping) mayvary as frequently as on a symbol by symbol basis.

The advanced modulation satellite receiver may be implemented tocommunicatively couple to an HDTV MPEG-2 (Motion Picture Expert Group)transport de-mux, audio/video decoder and display engine. The advancedmodulation satellite receiver and the HDTV MPEG-2 transport de-mux,audio/video decoder and display engine communicatively couple to a hostCPU (Central Processing Unit). The HDTV MPEG-2 transport de-mux,audio/video decoder and display engine also communicatively couples to amemory module and a conditional access functional block. The HDTV MPEG-2transport de-mux, audio/video decoder and display engine provides HD(High Definition) video and audio output that may be provided to an HDTVdisplay.

The advanced modulation satellite receiver may be implemented as asingle-chip digital satellite receiver supporting the decoder thatperforms decoding of LDPC coded signals via symbol decoding according tothe invention. The advanced modulation satellite receiver is operable toreceive communication provided to it from a transmitter device thatincludes an encoder as well.

In addition, several of the following Figures describe particularembodiments that may be used to implement some of the various aspects ofthe LDPC symbol decoding according to the invention. It is also notedthat the various aspects of LDPC symbol decoding described herein mayalso be extended to perform decoding of LDPC coded signals whose coderate and/or modulation (constellation and mapping) may vary asfrequently as on a symbol by symbol basis. Several details of thesevarious aspects are provided below.

FIG. 16 is a diagram illustrating an embodiment of an LDPC (Low DensityParity Check) code bipartite graph. An LDPC code may be viewed as beinga code having a binary parity check matrix such that nearly all of theelements of the matrix have values of zeros. For example,H=(h_(i,j))_(M×N) may be viewed as being a parity check matrix of anLDPC code with block length N. If every column of the matrix has d_(v)1's, and every row of the matrix has d_(c) 1's, then this code isreferred to as a (d_(v),d_(c)) regular LDPC code. For example, a regular(4,72) LDPC code would be viewed as being a code whose binary paritycheck matrix would have 4 1's in every column and 72 1 's in every row.These regular LDPC codes were introduced in R. Gallager, Low-DensityParity-Check Codes, Cambridge, Mass.: MIT Press, 1963.

A regular LDPC code can be represented as a bipartite graph by itsparity check matrix with left side nodes representing variable of thecode bits, and the right side nodes representing check equations. Thebipartite graph of the code defined by H may be defined by N variablenodes and M check nodes. Every variable node of the N variable nodes hasexactly d_(v) edges connecting this node to one or more of the checknodes (within the check M nodes). This number of d_(v) edges may bereferred to as the degree of a variable node. Analogously, every checknode of the M check nodes has exactly d_(c) edges connecting this nodeto one or more of the variable nodes. This number of d_(c) edges may bereferred to as the degree of a check node.

An edge between a variable node v_(i) and check node c_(j) may bedefined by e=(i, j). However, on the other hand, given an edge e=(i, j),the nodes of the edge may alternatively be denoted as by e=(v(e),c(e)).Given a variable node v_(i), one may define the set of edges emittingfrom the node v_(i) by E_(v)(i)={e|v(e)=i}. Given a check node c_(j),one may define the set of edges emitting from the node c_(j) byE_(c)(j)={e|c(e)=j}. Continuing on, the derivative result will be|E_(v)(i)|=d_(v) and |E_(c)(j)|=d_(c).

An irregular LDPC code may also described using a bipartite graph.However, the degree of each set of nodes within an irregular LDPC codemay be chosen according to some distribution. Therefore, for twodifferent variable nodes, v_(i) ₁ and v_(i) ₂ , of an irregular LDPCcode, |E_(v)(i₁) may not equal to |E_(v)(i₂)|. This relationship mayalso hold true for two check nodes. The concept of irregular LDPC codeswas originally introduced within M. Luby, M. Mitzenmacher, M. A.Shokrollahi, D. A. Spielman, and V. Stemann, “Practical Loss-ResilientCodes”, Proc. 29^(th) Symp. on Theory of Computing, 1997, pp. 150-159.

In general, with a graph of an LDPC code, the parameters of an LDPC codecan be defined by a degree of distribution, as described within M. Lugy,et al. (referenced above) and also within T. J. Richardson and R. L.Urbanke, “The capacity of low-density parity-check code undermessage-passing decoding,” IEEE Trans. Inform. Theory, Vol. 47, pp.599-618, Feb. 2001. This distribution may be described as follows:

Let λhd i represent the fraction of edges emanating from variable nodesof degree i and let ρ_(i) represent the fraction of edges emanating fromcheck nodes of degree i. Then, a degree distribution pair (λ,ρ) isdefined as follows:

${{\lambda(x)} = {{\sum\limits_{i = 2}^{M_{v}}{\lambda_{i}x^{i - 1}\mspace{14mu}{and}\mspace{14mu}{\rho(x)}}} = {\sum\limits_{i = 2}^{M_{c}}{\rho_{i}x^{i - 1}}}}},$where M_(v) and M_(c) represent the maximal degrees for variable nodesand check nodes, respectively.

From certain perspectives, the invention may be implemented withincommunication systems that involve combining modulation coding with LDPCcoding to generate LDPC coded signals. These LDPC coded signals may besuch that they have a code rate and/or modulation (constellation andmapping) that varies as frequently as on a symbol by symbol basis. Up tonow, there have been some attempts to combine modulation encoding withLDPC coding, yet they are all limited to employing only a single coderate or modulation (constellation and mapping) symbols generatedthereby. Nevertheless, some of the possible approaches to combinemodulation coding and LDPC coding are described below.

FIG. 17A is a diagram illustrating an embodiment of direct combining ofLDPC (Low Density Parity Check) coding and modulation encoding. A binarysequence (e.g., a bit stream) is provided to an LDPC (Low Density ParityCheck) encoder. The LDPC encoder introduces a degree of redundancy (orparity) within the bit sequence provided thereto. These LDPC coded bitsare then provided to a S/P (Serial to Parallel) path such that theoutput symbols may be provided to a modulation encoder. This S/P pathperforms the bit to m-bit symbol transformation. The modulation encoderoutputs a signal sequence that includes symbols (composed of LDPC codedbits) that correspond to a modulation having a constellation and amapping.

FIG. 17B is a diagram illustrating an embodiment of BICM (BitInterleaved Coded Modulation) that is employed in conjunction with LDPC(Low Density Parity Check) coding and modulation encoding. Thisembodiment is similar to the embodiment described above that performsdirect combining of LDPC coding and modulation encoding, with theexception that an interleaver is interposed between the LDPC encoder andthe modulation encoder.

A binary sequence (e.g., a bit stream) is provided to an LDPC encoder.The LDPC encoder introduces a degree of redundancy (or parity) withinthe bit sequence provided thereto. These LDPC coded bits are thenprovided to an interleaver to generate a degree of randomness within theLDPC coded bits thereby (hopefully) making that LDPC coded bit sequenceto be more robust to interference, noise, and other deleterious effects.This LDPC coded bit sequence that has been interleaved is then providedto a S/P (Serial to Parallel) path such that the output symbols may beprovided to a modulation encoder. Again, this S/P path performs the bitto m-bit symbol transformation. The modulation encoder outputs a signalsequence that includes symbols (composed of the interleaved LDPC codedbits) that correspond to a modulation having a constellation and amapping.

FIG. 17C is a diagram illustrating an embodiment of multilevel codedmodulation encoding. Rather than require a S/P (Serial to Parallel) pathbetween a single LDPC encoder and a modulation encoder, this embodimentshows a plurality of LDPC encoders operating in parallel such that theoutputs of each of the LDPC encoder is already within parallel format(thereby obviating the need for the S/P (Serial to Parallel) pathemployed within the embodiments described above). The outputs of theseLDPC encoders are provided to a modulation encoder. The modulationencoder outputs a signal sequence that includes symbols (composed of theLDPC coded bits provided by the various LDPC encoders) that correspondto a modulation having a constellation and a mapping.

All 3 of these embodiments, described above that perform the combinationof LDPC coding and modulation encoding, typically operate using a singlecode rate and also use a single modulation (constellation and mapping)to map the binary bits to a given constellation. That is to say, theyall typically employ a single code rate and a single modulation (havinga single constellation type and a single mapping) for that singleconstellation. This approach inherently limits the maximal performancethat may be achieved using these approaches. In contradistinction, theinvention is operable to operate on LDPC coded signals having a coderate and/or a modulation (constellation and mapping) that may vary asfrequently as on a symbol by symbol basis. To illustrate further thesingle modulation approach of these 3 embodiments, a specificimplementation that performs such a single mapping is described below.

FIG. 18 is a diagram illustrating an embodiment of a variable signalmapping LDPC (Low Density Parity Check) coded modulation system that isbuilt in accordance with invention. This embodiment shows how a generalimplementation may be made for mapping an LDPC block coded modulationsignal thereby generating LDPC coded signals having a modulation(constellation and mapping) that may vary as frequently as on a symbolby symbol basis.

In general, for any modulation, one can select as many as possibleconstellations and corresponding mappings, to construct an LDPC codedsignal having a modulation (constellation and mapping) that may vary asfrequently as on a symbol by symbol basis. This diagram illustrates apossible implementation for an m-bit constellation modulation. Moreover,it is also noted that the code can be any one of a variety of blockcodes.

In a very general illustration, a plurality of different encoders isemployed. A first encoder employs a part 1 of a codeword, a secondencoder employs a part 2 of a codeword, . . . , and a final encoder (ofthe plurality of encoders) employs a part m of a codeword. Those symbolsthat satisfy a condition 1 are provided to a map I1. Similarly, thosesymbols that satisfy a condition 2 are provided to a map I2, and thosesymbols that satisfy a condition N are provided to a map IN. The variousconditions employed to govern the direction of which mapping to whichthe symbols are provided may be selected by a designer implementing theinvention.

The signal sequence generated by this embodiment, or any of the otherembodiments for which the decoding approaches of the invention mayoperate, may be a variable code rate and/or a variable modulationsignal. For example, the code rate of the symbols of the signal sequencemay vary as frequently as on a symbol by symbol basis. A first symbolmay be encoded according to a first code rate, and a second symbol maybe encoded according to a second code rate.

In addition, the modulation of the symbols of the signal sequence mayvary as frequently as on a symbol by symbol basis. More specifically,for the variable modulation type signal, either one or both of theconstellation or mapping of the symbols of the signal sequence may varyas frequently as on a symbol by symbol basis. As yet another example,multiple symbols of the signal sequence may all be mapped to a similarlyshaped constellation, yet various symbols may also have differentmappings to the same constellation. As one specific example, two symbolsmay each be associated with an 8 PSK (8 Phase Shift Key) shapedconstellation, yet each of the symbols may be mapped differently withinthat 8 PSK shaped constellation. Clearly, other types of modulations mayalso be employed without departing from the scope and spirit of theinvention.

FIG. 19 is a diagram illustrating an embodiment of LDPC (Low DensityParity Check) coded modulation decoding functionality using bit metricaccording to the invention. To perform decoding of an LDPC codedmodulation signal having an m-bit signal sequence, the functionality ofthis diagram may be employed. After receiving the I,Q (In-phase,Quadrature) values of a signal at the symbol nodes, an m-bit symbolmetric computer functional block calculates the corresponding symbolmetrics. At the symbol nodes, these symbol metrics are then passed to asymbol node calculator functional block that uses these received symbolmetrics to calculate the bit metrics corresponding to those symbols.These bit metrics are then passed to the bit nodes connected to thesymbol nodes.

Thereafter, at the bit nodes, a bit node calculator functional blockoperates to compute the corresponding soft messages of the bits. Then,in accordance with iterative decoding processing, the bit nodecalculator functional block receives the edge messages from a check nodeoperator functional block and updates the edge messages with the bitmetrics received from the symbol node calculator functional block. Theseedge messages, after being updated, are then passed to the check nodeoperator functional block.

At the check nodes, the check node operator functional block thenreceives these edge messages sent from the bit nodes (from the bit nodecalculator functional block) and updates them accordingly. These updatededge messages are then passed back to the bit nodes (e.g., to the bitnode calculator functional block) where the soft information of the bitsis calculated using the bit metrics and the current iteration values ofthe edge messages. Thereafter, using this just calculated softinformation of the bits (shown as the soft message), the bit nodecalculator functional block updates the edge messages using the previousvalues of the edge messages (from the just previous iteration) and thejust calculated soft message. The iterative processing continues betweenthe bit nodes and the check nodes according to the LDPC code bipartitegraph that was employed to encode the signal that is being decoded.

These iterative decoding processing steps, performed by the bit nodecalculator functional block and the check node operator functionalblock, are repeated a predetermined number of iterations (e.g., repeatedn times, where n is selectable). Alternatively, these iterative decodingprocessing steps are repeated until the syndromes of the LDPC code areall equal to zero (within a certain degree of precision).

Soft output information is generated within the bit node calculatorfunctional block during each of the decoding iterations. In thisembodiment, this soft output may be provided to a hard limiter wherehard decisions may be made, and that hard information may be provided toa syndrome calculator to determined whether the syndromes of the LDPCcode are all equal to zero (within a certain degree of precision). Whenthy are not, the iterative decoding processing continues again byappropriately updating and passing the edge messages between the bitnode calculator functional block and the check node operator functionalblock.

After all of these iterative decoding processing steps have beenperformed, then the best estimates of the bits are output based on thebit soft information. In the approach of this embodiment, the bit metricvalues that are calculated by the symbol node calculator functionalblock are fixed values and used repeatedly in updating the bit nodevalues.

FIG. 20 is a diagram illustrating an alternative embodiment of LDPCcoded modulation decoding functionality using bit metric according tothe invention (when performing n number of iterations). This embodimentshows how the iterative decoding processing may be performed when apredetermined number of decoding iterations, shown as n, is performed.If the number of decoding iterations is known beforehand, as in apredetermined number of decoding iterations embodiment, then the bitnode calculator functional block may perform the updating of itscorresponding edge messages using the bit metrics themselves (and notthe soft information of the bits as shown in the previous embodiment anddescribed above). This processing may be performed in all but the lastdecoding iteration (e.g., for iterations 1 through n−1). However, duringthe last iteration, the bit node calculator functional block calculatedthe soft information of the bits (shown as soft output). The soft outputis then provided to a hard limiter where hard decisions may be made ofthe bits. The syndromes need not be calculated in this embodiment sinceonly a predetermined number of decoding iterations are being performed.

FIG. 21 is a diagram illustrating an alternative embodiment of LDPC (LowDensity Parity Check) coded modulation decoding functionality using bitmetric (with bit metric updating) according to the invention. To performdecoding of an LDPC coded modulation signal having an m-bit signalsequence, the functionality of this diagram may be employed. Afterreceiving the I,Q (In-phase, Quadrature) values of a signal at thesymbol nodes, an m-bit symbol metric computer functional blockcalculates the corresponding symbol metrics. At the symbol nodes, thesesymbol metrics are then passed to a symbol node calculator functionalblock that uses these received symbol metrics to calculate the bitmetrics corresponding to those symbols. These bit metrics are thenpassed to the bit nodes connected to the symbol nodes. The symbol nodecalculator functional block is also operable to perform bit metricupdating during subsequent decoding iterations.

Thereafter, at the bit nodes, a bit node calculator functional blockoperates to compute the corresponding soft messages of the bits. Then,in accordance with iterative decoding processing, the bit nodecalculator functional block receives the edge messages from a check nodeoperator functional block and updates the edge messages with the bitmetrics received from the symbol node calculator functional block. Thisupdating of the edge messages may be performed using the updated bitmetrics during subsequent iterations. These edge messages, after beingupdated, are then passed to the check node operator functional block.

At the check nodes, the check node operator functional block thenreceives these edge messages sent from the bit nodes (from the bit nodecalculator functional block) and updates them accordingly. These updatededge messages are then passed back to the bit nodes (e.g., to the bitnode calculator functional block) where the soft information of the bitsis calculated using the bit metrics and the current iteration values ofthe edge messages. Thereafter, using this just calculated softinformation of the bits (shown as the soft message), the bit nodecalculator functional block updates the edge messages using the previousvalues of the edge messages (from the just previous iteration) and thejust calculated soft message. At the same time, as the just calculatedsoft information of the bits (shown as the soft message) has beencalculated, this information may be passed back to the symbol nodes(e.g., to the symbol node calculator functional block) for updating ofthe bit metrics employed within subsequent decoding iterations. Theiterative processing continues between the bit nodes and the check nodesaccording to the LDPC code bipartite graph that was employed to encodethe signal that is being decoded (by also employing the updated bitmetrics during subsequent decoding iterations).

These iterative decoding processing steps, performed by the bit nodecalculator functional block and the check node operator functionalblock, are repeated a predetermined number of iterations (e.g., repeatedn times, where n is selectable). Alternatively, these iterative decodingprocessing steps are repeated until the syndromes of the LDPC code areall equal to zero (within a certain degree of precision).

Soft output information is generated within the bit node calculatorfunctional block during each of the decoding iterations. In thisembodiment, this soft output may be provided to a hard limiter wherehard decisions may be made, and that hard information may be provided toa syndrome calculator to determined whether the syndromes of the LDPCcode are all equal to zero (within a certain degree of precision). Whenthy are not, the iterative decoding processing continues again byappropriately updating and passing the edge messages between the bitnode calculator functional block and the check node operator functionalblock.

After all of these iterative decoding processing steps have beenperformed, then the best estimates of the bits are output based on thebit soft information. In the approach of this embodiment, the bit metricvalues that are calculated by the symbol node calculator functionalblock are fixed values and used repeatedly in updating the bit nodevalues.

FIG. 22 is a diagram illustrating an alternative embodiment of LDPCcoded modulation decoding functionality using bit metric (with bitmetric updating) according to the invention (when performing n number ofiterations). This embodiment shows how the iterative decoding processingmay be performed when a predetermined number of decoding iterations,shown as n, is performed (again, when employing bit metric updating). Ifthe number of decoding iterations is known beforehand, as in apredetermined number of decoding iterations embodiment, then the bitnode calculator functional block may perform the updating of itscorresponding edge messages using the bit metrics/updated bit metricsthemselves (and not the soft information of the bits as shown in theprevious embodiment and described above). This processing may beperformed in all but the last decoding iteration (e.g., for iterations 1through n−1). However, during the last iteration, the bit nodecalculator functional block calculated the soft information of the bits(shown as soft output). The soft output is then provided to a hardlimiter where hard decisions may be made of the bits. The syndromes neednot be calculated in this embodiment since only a predetermined numberof decoding iterations are being performed.

FIG. 23A is a diagram illustrating bit decoding using bit metric (shownwith respect to an LDPC (Low Density Parity Check) code bipartite graph)according to the invention. Generally speaking, after receiving I, Qvalues of a signal at a symbol nodes, the m-bit symbol metrics arecomputed. Then, at the symbol nodes, the symbol metric is used tocalculate the bit metric. The bit metric is then passed to the bit nodesconnected to the symbol nodes. At the bit nodes, the soft messages ofthe bits are computed, and they are used to update the edge message sentfrom the check nodes with the bit metric. These edge messages are thenpassed to the check nodes. At the check nodes, updating of the edgemessages sent from the bit nodes is performed, and these values are passback the bit nodes.

As also described above with respect to the corresponding functionalityembodiment, after all of these iterative decoding processing steps havebeen performed, then the best estimates of the bits are output based onthe bit soft information. In the approach of this embodiment, the bitmetric values that are calculated by the symbol node calculatorfunctional block are fixed values and used repeatedly in updating thebit node values.

FIG. 23B is a diagram illustrating bit decoding using bit metricupdating (shown with respect to an LDPC (Low Density Parity Check) codebipartite graph) according to the invention. With respect to this LDPCcode bipartite graph that performs bit metric updating, the decodingprocessing may be performed as follows:

After receiving the I, Q value of the signal at the symbol nodes, them-bit symbol metrics are computed. Then, at the symbol nodes, the symbolmetrics are used to calculate the bit metrics. These values are thenpassed to the bit nodes connected to the symbol nodes. At the bit nodes,the edge message sent from the check nodes are updated with the bitmetrics, and these edge messages are passed to the check nodes. Inaddition, at the same time the soft bit information is updated andpassed back to the symbol nodes. At the symbol nodes, the bit metricsare updated with the soft bit information sent from the bit nodes, andthese values are passed back to the variable nodes. At the check nodes,the edge information sent from the bit nodes is updated, and thisinformation is passed back to the bit nodes.

As also described above with respect to the corresponding functionalityembodiment, after all of these iterative decoding processing steps havebeen performed, then the best estimates of the bits are output based onthe bit soft information. Again, it is shown in this embodiment that thebit metric values are not fixed; they are updated for use withinsubsequent decoding iterations. This is again in contradistinction tothe embodiment described above where the bit metric values that arecalculated only once and remain fixed values for all of the decodingiterations.

FIG. 24A is a diagram illustrating an LDPC (Low Density Parity Check)coded modulation tripartite graph with symbol nodes connected to bitnodes according to the invention. In this embodiment, it can be seenthat the bit nodes are connected to the symbol nodes. The appropriatelycorresponding bit nodes are also connected to the check nodes accordingto the LDPC code being employed. However, it is noted that the symbolsto be decoded are solely determined by the bits connected to thecorresponding symbol. This property is capitalized upon such that thebit nodes may be removed from the LDPC tripartite graph, so that thesymbol nodes may be directly connected to the check nodes therebygenerating an LDPC coded modulation bipartite graph.

As one example, 3 symbol nodes, s₀,s₁,s₂, are connected to the 9 bitnodes, b₀,b₁,b₂, . . . , b₈, according to the following mapping:s₀

(b₀,b₃,b₆)s₁

(b₁,b₄,b₇)s₂

(b₂,b₅,b₈)  (EQ 1)

The connections between the 9 bit nodes, b₀,b₁,b₂, . . . , b₈, and the 3check nodes, c₀,c₁,c₂, are made according to the following mapping:b₀

(c₀,c₂)b₁

(c₀,c₁)b₂

(c₁,c₂)b₃

(c₀,c₁)b₄

(c₁,c₂)b₅

(c₀,c₂)b₆

(c₀,c₁)b₇

(c₁,c₁)b₈

(c₀,c₁)

FIG. 24B is a diagram illustrating an LDPC (Low Density Parity Check)coded modulation bipartite graph with symbol nodes connected directly tocheck nodes according to the invention (this bipartite graph isgenerated from the tripartite graph shown in FIG. 24A). One aspect ofthe invention is the ability to reduce the number of nodes within anLDPC bipartite graph by directly connecting the symbols nodes to thecheck nodes (e.g., by modifying an LDPC coded modulation tripartitegraph to generate an LDPC coded modulation bipartite graph). However,this must be performed very carefully to ensure proper decoding of suchLDPC coded signals. As is described herein, the labeling of the edgesconnected the symbols nodes to the check nodes needs to be donecarefully to ensure proper decoding of symbols.

Within this LDPC code bipartite graph, the edges are only connectedbetween the symbol nodes and the check nodes. In doing so, every edgeconnecting the symbol nodes and the check nodes is labeled by a valueaccording to EQ 1 shown above. In some embodiments, these edges arelabeled using octal values.

For example, using an octal labeling approach, the edge connecting thesymbol node s₀ to the check node c₀, depicted as (s₀,c₀), is labeled as7 since all three bits b₀,b₃,b₆ are connected to c₀ (e.g., labeled as 7because b₀,b₃,b₆=111). Similarly, the edge connecting the symbol node s₀to the check node c₁, depicted as (s₀,c₁), is labeled as 6 since onlythe two bits b₀,b₃ are connected to c₁ (e.g., labeled as 6 becauseb₀,b₃,b₆=110). As another example,, the edge connecting the symbol nodes₀ to the check node c₂, depicted as (s₀,c₂), is labeled as 1 since onlythe one bit b₀ is connected to c₂ (e.g., labeled as 1 becauseb₀,b₃,b₆=100). The additional edges that communicatively couple thesymbols nodes to the check nodes may also be labeled according to thisconvention.

One of the advantages of the symbol node to check node LDPC codebipartite graph is that a decoder may use symbol metrics when performingthe decoding processing of the LDPC coded symbols instead of bitmetrics. In this way of performing the decoding processing, there istherefore no need to perform metric updating; the metric updating withinthe decoding processing may have the undesirable effect of requiring anincreased amount of memory to be used. Moreover, the decoding based onthe LDPC code bipartite graph (sometimes referred to as a symbol LDPCcode bipartite graph) actually out-performs decoding processing that isbased on an LDPC code tripartite graph (whose bit nodes are connected tocheck nodes). In addition, the LDPC symbol decoding provides comparableor better performance of LDPC bit decoding that involves updating of thebit metrics.

FIG. 25A is a diagram illustrating symbol decoding (shown with respectto an LDPC (Low Density Parity Check) coded modulation bipartite graph)according to the invention. The symbol decoding processing performedaccording to the invention may be performed using an LDPC codedmodulation bipartite graph in which the symbol nodes are connecteddirectly to the check nodes. In general, the I,Q values of a symbol areprovided to the symbol nodes, and the iterative decoding processing isperformed according to the manner in which the labeled edgescommunicatively couple the symbol nodes to the check nodes.

As an example of how the decoding processing may be performed using suchan LDPC coded modulation bipartite graph, a rate ⅔ LDPC code with an 8PSK (8 Phase Shift Key) modulation signal is decoded and explained indetail. This LDPC code may be a regular LDPC code or an irregular LDPCcode without departing from the scope and spirit of the invention. Theblock length of the LDPC code is 3N and a 3 bit symbol s_(i) is mapped(e.g., using a symbol mapper) according to the following notation:s _(i)=(b _(i) ,b _(N+i) ,b _(2N+i))

The parity check matrix of the LDPC code may be represented as[h_(ij)]_(N×3N). The estimated symbols r_(i) corresponding to the 3 bitsymbol s_(i) may be represented as r_(i)=(r_(0i),r_(1i),r_(2i)). Thepartial syndromes S^(m)(i) and S_(m)(i) that are calculated using theestimated symbols and the parity check matrix of the LDPC code may berepresented as follows:

$\begin{matrix}{{{S^{m}(i)} = {\sum\limits_{j = 0}^{m - 1}( {{r_{0j}h_{ij}} + {r_{1j}h_{i{({N + j})}}} + {r_{2j}h_{i{({{2N} + j})}}}} )}}{{S_{m}(i)} = {\sum\limits_{j = m}^{N - 1}( {{r_{0j}h_{ij}} + {r_{1j}h_{i{({N + j})}}} + {r_{2j}h_{i{({{2N} + j})}}}} )}}} & ( {{EQ}\mspace{20mu} 2} )\end{matrix}$

The following decoding processing description is described as beingperformed on a signal sequence Y. The probability of the signal sequenceY satisfying the partial syndrome, p(S^(j)(i)=m|Y), to be equal toA_(i,j)(m) is calculated (e.g., the probability ofp(S^(j)(i)=m|Y)=A_(i,j)(m)). In addition, other probabilities arecalculated; namely, the probability of the signal sequence Y satisfyingthe partial syndrome, p(S_(j)(i)=m|Y), to be equal to B_(i,j)(m) iscalculated (e.g., the probability of p(S_(j)(i)=m|Y)=B_(i,j)(m)). Theseprobabilities are all calculated based on the following conditions:A _(i,0)(0)=1B _(i,deg() c _(i) ⁾⁻¹(0)=1, andA _(i,0)(m)=0B _(i,deg(c) _(i) ⁾⁻¹(m)=0, where m≠0.

Since the decoding may be performed in the logarithmic domain therebyenabling multiplication operations to be performed using addition anddivision operations to be performed using subtraction, these variablesmay be redefined within the logarithmic domain as follows:α_(i,j)(m)=log(A _(i,j)(m))β_(i,j)(m)=log(B _(i,j)(m))

These values may be referred to as the alphas, or forward metrics,(α_(i,j)(m)) and betas, or backward metrics, (β_(i,j)(m)) to be employedwithin the decoding processing.

The edge messages being passed from the check nodes to the symbol nodesmay be represented as Medge[i][j][k], where i runs according to theappropriately labeled edges within the LDPC coded modulation bipartitegraph.

As some examples:

1. if the label is 7, then k runs from 0 to 7,

2. if the label is 3, 5, or 6, then k runs from 0 to 3, and

3. if the label is 1, 2, or 6, then k runs between 0 to 1.

In addition, a new function x(v) that varies from {0, . . . ,7} to {0,1}may be employed. The value v may be viewed as being an integerrepresented in octal. Then, the value of v may be represented asv=(v₀,v₁, v₂). This new function x(v) may be represented as follows:x(v)=v ₀⊕v₁⊕v₂  (EQ 3)

where ⊕ is an exclusive-or function (e.g., binary addition).

The notation and definitions provided above are also employed todescribe the symbol decoding processing in other embodiments whosedecoding processing and/or functionality are described in more detailbelow. More specifically, the embodiments described in more detail belowshow how the check node updating and symbol sequence estimation, as wellas symbol node updating, is performed using these various values.

FIG. 25B is a diagram illustrating an embodiment of symbol decodingfunctionality (supported with an LDPC (Low Density Parity Check) codedmodulation bipartite graph) according to the invention. This embodimentshows in more detail how the check node updating and symbol sequenceestimation, as well as symbol node updating, is performed.

The decoding processing described in this embodiment may be betterunderstood in the context of the check node updating and symbol sequenceestimation, including the symbol node updating, that may be performedwithin in at least 2 different embodiments that are described herein inaccordance with the invention: (1) symbol decoding and (2) hybriddecoding (that performs a combination of bit level and symbol leveldecoding). One possible embodiment of symbol decoding is described inthis diagram (FIG. 25B), and one possible embodiment of the hybriddecoding is described below with respect to the diagram of FIG. 27.

Beginning from the left hand side of the diagram, input informationcorresponding to the calculated partial syndromes, that also includesthe initial values of the alphas (α_(i,j)(m)) and the betas (β_(i,j)(m))(e.g., forward and backward metrics), are provided to a check nodeupdate functional block. Iterative decoding processing is performedwithin the check node update functional block over the total number ofcheck nodes. For example, M iterations are performs over i (where ivaries from 0 to M−1, and where M is the total number of check nodes ofthe LDPC bipartite graph).

In doing this iterative decoding processing, the check node updatinginitially involves calculating the values of the alphas α_(i,j)(m)) andthe betas (β_(i,j)(m)) (beyond merely the initial values that areprovided during the initial iteration) for each of the symbols of areceived symbol block. This iterative decoding processing in calculatingthe alphas and betas may be performed using a forward-backward procedurethrough the received symbol block.

The calculation of the alphas and betas is described below.

For j=0 to deg(c_(i))−1 and m=0,1, the forward-backward processingprocedure may be employed to calculate the alphas (α_(i,j)(m)) and thebetas (β_(i,j)(m)) as follows:α_(i,j)(m)=min*{Medge[i][j−1][k]+α _(i,j−1)(m⊕x(k))| all possible k}β_(i,j)(m)=min*{Medge[i][j+1][k]+β_(i,j+1)(m⊕x(k))| all possible k}

Now that these values of alpha and beta are available for each of thesymbols within a received symbol block, the edge messages Medge[i][j][k](that communicatively couple the symbol nodes to the check nodes) areupdated using these calculated alphas and betas values.

For j=0 to deg(c_(i))−1 and all possible k, the updating of the edgemessages Medge[i][j][k] may be performed as follows:Medge[i][j][k]=min*{└α_(i,j)(0)+β_(i,j)(x(k))┘,└α_(i,j)(1)+β_(i,j)(x(k)⊕1)┘}

The min* processing functionality described herein may be betterunderstood by the following description. The min* processing includesdetermining a minimum value from among two values (e.g., shown asmin(A,B) in min* processing) as well as determining a logarithmiccorrection factor (e.g., shown as ln(1+e^(−|A−B|)) in min* processing)in selecting the smaller metric. In addition, it is also noted that max*processing may alternatively be performed in place of min* processing.The max* processing operation also includes a logarithmic correction inselecting the larger metric. It is noted that the various embodiments ofthe invention may be implemented using the max* operations in lieu ofthe min* operation when preferred in a given implementation.

The min* processing, when operating on inputs A and B, may be expressedas follows:min*(A, B)=min(A, B)-ln(1+e ^(−|A−B|))

Again, the min* processing may alternatively be performed using max*processing. The max* processing, when operating on inputs A and B, maybe expressed as follows:max*(A, B)=max(A, B)+ln(1+e ^(−|A−B|))

Moreover, when multiple min* operations are to be performed on multiplevalues (e.g., more than 2), the min* processing may be expressed asfollows:min*(x ₁ , . . . , x _(N))=min*(min*(x ₁ , . . . ,x _(N−1)),x _(N))  (EQ4)

After the check node processing has been completed, a symbol sequenceestimate and symbol node update functional block operates using thecheck node update messages to continue the decoding processing.

Since the total number of edges is the same count from either side(e.g., from either the symbol node side or the check node side), theedges are intrinsically re-ordered according to the symbols that arebeing decoded. This re-ordering may be intrinsically performed using aLUT (Look-Up Table) to ensure the proper ordering of the check nodeupdating. In other words, the LUT may be implemented to perform thefunction of which edge information to take when performing the symbolsequence estimate and symbol node update. In addition, this re-orderingfunctionality may be inherently implemented in hardware for properordering of the check node updating such that it corresponds to an orderthat is appropriate to the symbol node updating. For proper decoding ofthe symbols of the sequence (e.g., first symbol to last symbol), thereneeds to be some ordering of the symbols. However, this symbol orderingis not critical when performing the check node updating. That is to say,the ordering of the check node updating may then be performed accordingto any desired ordering, and to ensure proper decoding of the symbolsaccording to the desired order (e.g., first symbol to last symbol), thecheck node updating is performed to ensure that the edge messages areinherently appropriately ordered according to the desired order for thedecoding processing.

More specifically, this decoding processing may be understood withrespect to the edge messages Medge[i][j][k], where i runs across all ofthe symbol nodes, where j runs according to the degree of the edges fromthe symbol nodes, and where k runs according to the labels of the LDPCbipartite graph.

This embodiment described with respect to this diagram is shown withrespect to a code that includes 3 bit symbols, coded according to 8 PSK(8 Phase Shift Key) modulation. However, it is noted that such adecoding approach may also be adapted very easily to decoding signalshaving an even larger number of bits. For example, this decodingapproach may be adapted to perform decoding of signals having symbols ofhigher order modulations including 16 QAM (16 Quadrature AmplitudeModulation), 16 APSK (16 Asymmetric Phase Shift Keying), 64 QAM, andeven other modulation types without departing from the scope and spiritof the invention.

The label on the j -th edge from the check node i may be denoted asL_(i,j). A new function, sh(L,v), may be defined and employed to assistin the decoding processing describer herein. This new function sh(L,v)may be defined as follows:

$\begin{matrix}{{{sh}( {L,( {v_{0},v_{1},v_{2}} )} )} = \{ \begin{matrix}v_{2} & {L = 1} \\v_{1} & {L = 2} \\( {v_{1},v_{2}} ) & {L = 2} \\v_{0} & {L = 4} \\( {v_{0},v_{2}} ) & {L = 5} \\( {v_{0},v_{1}} ) & {L = 6} \\( {v_{0},v_{1},v_{2}} ) & {L = 7}\end{matrix} } & ( {{EQ}\mspace{20mu} 5} )\end{matrix}$

After the edge messages have been intrinsically and appropriatelyre-ordered using the approach described above, the symbol sequenceestimate and symbol node update functional block continues to operateaccording to the following procedure.

For m=0, . . . ,7, the possible values for the soft symbol estimates arecomputed (e.g., the possible values for the soft information of thesymbols is calculated) as follows:

${{p_{i}(m)} = {{{Metric}_{i}\lbrack m\rbrack} + {\sum\limits_{j = 0}^{{\deg{(s_{i})}} - 1}( {\sum\limits_{L_{i,j}}{{{{Medge}\lbrack i\rbrack}\lbrack j\rbrack}\lbrack {{sh}( {L_{i,j},m} )} \rbrack}} )}}},$where Metric_(i)[m] is the appropriate symbol metric obtained from thereceived signal according to its appropriate modulation (constellationand mapping values).

The symbol sequence estimate and symbol node update functional blockcontinues by estimating the symbols using the soft symbol estimates.More specifically, the estimate of the symbol s_(i) to m is made suchthat p_(i)(m) is the smallest value selected from among all of thepossible values of p_(i)(0), p(1), . . . ,p_(i)(7).

After the estimate of the symbols is made using the soft symbolestimates, the edge messages are updated within the symbol sequenceestimate and symbol node update functional block using the older edgemessages. More specifically, the edge message are updated as follows:

The processing may be better understood by considering the edge labelL_(i,j),

1. if L_(i,j)=7, then for m=0, . . . , 7,Medge[i][j][k]=p_(i)[m]-Medge[i][j][m].

2. alternatively, if L_(i,j)=3,5,6, then for m₀,m_(i)∈{0,1}, then thevalues of the edge messages may be defined as:

${{{{Medge}\lbrack i\rbrack}\lbrack j\rbrack}\lbrack ( {m_{0},m_{1}} ) \rbrack} = \{ \begin{matrix}{{\min^{*}( {{p_{i}( {0,m_{0},m_{1}} )},{p_{i}( {1,m_{0},m_{1}} )}} )} - {{{{Medge}\lbrack i\rbrack}\lbrack j\rbrack}\lbrack ( {m_{0},m_{1}} ) \rbrack}} & {L_{i,j} = 3} \\{{\min^{*}( {{p_{i}( {m_{0},0,m_{1}} )},{p_{i}( {m_{0},1,m_{1}} )}} )} - {{{{Medge}\lbrack i\rbrack}\lbrack j\rbrack}\lbrack ( {m_{0},m_{1}} ) \rbrack}} & {L_{i,j} = 5} \\{{\min^{*}( {{p_{i}( {m_{0},m_{1},0} )},{p_{i}( {m_{0},m_{1},1} )}} )} - {{{{Medge}\lbrack i\rbrack}\lbrack j\rbrack}\lbrack ( {m_{0},m_{1}} ) \rbrack}} & {L_{i,j} = 6}\end{matrix} $

3. alternatively, if L_(i,j)=1,2,4, then for m=0,1, then the values ofthe edge messages may be defined as:

${{{{Medge}\lbrack i\rbrack}\lbrack j\rbrack}\lbrack (m) \rbrack} = \{ \begin{matrix}{ {{\min^{*}{\{ {p_{i}( {k_{0},k_{1},m} )} k_{0}}},{k_{1} \in \{ {0,1} \}}} \} - {{{{Medge}\lbrack i\rbrack}\lbrack j\rbrack}\lbrack m\rbrack}} & {L_{i,j} = 1} \\{ {{\min^{*}{\{ {p_{i}( {k_{0},m,k_{1}} )} k_{0}}},{k_{1} \in \{ {0,1} \}}} \} - {{{{Medge}\lbrack i\rbrack}\lbrack j\rbrack}\lbrack m\rbrack}} & {L_{i,j} = 2} \\{ {{\min^{*}{\{ {p_{i}( {m,k_{0},k_{1}} )} k_{0}}},{k_{1} \in \{ {0,1} \}}} \} - {{{{Medge}\lbrack i\rbrack}\lbrack j\rbrack}\lbrack m\rbrack}} & {{L_{i,j} = 4},}\end{matrix} $

where the right hand side edge of these equations is the old edgemessage passed from the check node.

Continuing on with the iterative decoding processing, using the updatededge messages (that are updated either a predetermined number of timesand/or until convergence of the edge messages has been met within acertain degree of precision), then the best estimates of the symbols ofa received symbol block may be made.

The performance of various approaches to decoding such a received symbolblock are compared in the following diagram.

FIG. 26 is a diagram illustrating an embodiment of performancecomparison of symbol vs. bit decoding of LDPC (Low Density Parity Check)code modulation signals according to the invention. These performancecurves are described in the context of BER (Bit Error Rate) versusE_(b)/N_(o) (ratio of energy per bit E_(b) to the Spectral Noise DensityN_(o)). This term E_(b)/N_(o) is the measure of SNR (Signal to NoiseRatio) for a digital communication system. When looking at theseperformance curves, the BER may be determined for any given E_(b)/N_(o)(or SNR).

Three different decoding approaches are compared when decoding LDPCcoded modulation signals. Within this comparison, the block size of theLDPC code is 14400, and the signal is a code rate ⅔8 PSK (8 Phase ShiftKey) LDPC coded modulation signal.

As some example, the worst performing performance curve corresponds tobit decoding only; when operating at an E_(b)/N_(o) of approximately 3.5dB (decibels), the BER of the bit decoding only approach isapproximately 2.5×10⁻⁶.

The next better performance curve corresponds to performing bit decodingin accompany with bit metric updating; for this decoding approach, whenoperating at an E_(b)/N_(o) of approximately 3.5 dB, the BER of the bitdecoding approach (that also included metric updating) decreases evenmore to below approximately under 2×10⁻⁷.

However, the symbol decoding approach described herein provides a betterperformance than either of these other approaches. More specifically,for this symbol decoding approach performed in accordance with theinvention, when operating at an E_(b)/N_(o) of approximately 3.5 dB, theBER of the symbol decoding approach decreases by an even greater amountto approximately 1×10⁻⁷.

As can be seen when comparing these various approaches to performingdecoding of LDPC coded modulation signals, the symbol decoding approachmay be implemented as to provide for much improved performance.

FIG. 27 is a diagram illustrating an embodiment of hybrid decodingfunctionality that reduces the complexity of symbol decoding of LDPCcoded modulation signals according to the invention.

This hybrid approach to performing decoding of LDPC coded modulationsignals is similar to the symbol decoding approach described abovewithin other embodiments with the exception being that the check nodesare updated using the edge messages corresponding to the bit nodes andthe symbol nodes are updated using the symbol metrics and the combinededge messages corresponding to the bit nodes.

With respect to the LDPC code bipartite graphs described above, it isnoted that the labels of some of the edges correspond to more than 1bit. For example, for the bits 3, 5, 6, and 7, the edge messagescorrespond to more than 2 values. Because of this, the common approachof employing LLR (log likelihood ratio) decoding cannot be employed.Moreover, additional memory may be required to store the increasednumber of edge messages that are employed when performing symboldecoding.

The hybrid approach to LDPC coded modulation decoding may be employed toreduce the increase of complexity that may be associated with someimplementations of symbol decoding of LDPC coded modulation signals.

The hybrid decoding approach may be characterized as follows:

1. updating the check nodes using the bit edge messages, and

2. updating the symbol nodes using the symbol metrics and the combinedbit edge message.

Within this diagram, a modified check node update functional block and asymbol sequence estimate and symbol node update functional block areemployed; these functional blocks (for the hybrid decodingfunctionality) are modified with respect to the symbol decodingfunctionality described above. This diagram is shown as receiving inputthat includes the partial syndrome information.

A check node update functional block performs updating of the edgemessages therein. Initially, during a first decoding iteration, thecheck node update functional block calculates the edge messages for thisfirst decoding iteration. These edge messages are then passed to asymbol sequence estimate and symbol node update functional block.

Within the symbol sequence estimate and symbol node update functionalblock and similar to the embodiment described above, since the totalnumber of edges is the same count from either side (e.g., from eitherthe symbol node side or the check node side), the edges are inherentlyordered in a manner that is appropriate for the decoding. As alsodescribed above, this appropriate ordering may be implemented accordingto a LUT, or it may be inherently implemented in hardware. Again, theordering of the decoded signal is what is important; the order in whichthe check nodes are processed is not critical (they may be processed inan order that corresponds to the order in which the signal is to bedecoded).

The symbol sequence estimate and symbol node update functional blockcontinues by computing soft symbol estimates and by estimating thesymbols using those calculated soft symbol estimates. Within the symbolsequence estimate and symbol node update functional block, afterobtaining the soft symbol estimate p_(i)[m] from the symbol node update,min* processing may be employed to decompose the soft symbol estimatesto soft bit estimates for every edge (based on the labels of the edges).An example of this processing may be employed to understand the decodingprocessing by considering the j -th edge of the i -th symbol as havingthe label 5. This symbol then has 2 bits connected to the check nodethrough this edge. The soft bit estimates for the k -th bit may becalculated as follows:est _(i,j,0) [b]=min*{p _(i)(m ₀ ,m ₁ ,b)|m ₀ ,m ₁∈{0,1}}  (EQ 6)est _(i,j,1) [b]=min*{p _(i)(b,m ₀ ,m ₁)|m ₀ ,m ₁∈{0,1}}  (EQ 7)

The bit estimates are then made corresponding to these soft bitestimates. Using these soft bit estimates, the bit edge messages arethen updated using the symbol metric and the combined bit edge messages.Once these bit edge messages are updated, they may then be passed to thecheck nodes to continue the subsequent iterations of the iterativedecoding processing. Using this approach, memory can be reduced (whencompared to the symbol decoding approach) and the LLR decoding approachmay be performed in updating the check nodes.

Continuing on with the iterative decoding processing, the edge messagesare then updated using the updated bit edge messages. The iterativedecoding processing continues for a predetermined number of iterationsor until the edge messages have converged to a solution within anacceptable degree of precision. Best estimates of the symbols of areceived symbol block may then be made after the iterative decodingprocessing has been performed in a similar manner than in performedabove with respect to the symbol decoding approach.

Some comments may be made when comparing the symbol decoding approach,the bit only decoding approach, the bit (with metric updating) decodingapproach, and the hybrid decoding approach. When updating of the symbolnodes is performed using symbol metrics, the edge messages for thesymbols are needed. Therefore, the decoding processing has first to getback the edge message of the symbol from the edge message of the bits.Since the bit edge message is a probability of the bit related to thecheck node, then the conditional probability is needed to get the symbolprobability. However, that probability is initially not available.Therefore, the decoding processing assumes that those bits areindependent from one another. While this property does hold true for theinformation bits of the LDPC code, it is not necessarily true for thecheck bits. Because of this characteristic of the hybrid decodingapproach, the hybrid decoding approach may incur some performance losswhen compared to the other approaches of decoding described herein.

FIG. 28A is a flowchart illustrating an embodiment of a method forsymbol decoding of LDPC coded modulation signals according to theinvention. The method involves receiving a symbol block that includes aplurality of symbols. This symbol block may be viewed as being a blockof LDPC coded modulation symbols. The symbols are then mapped accordingto an appropriate code rate and/or modulation. The modulation includes aconstellation and a mapping for each symbol within the symbol block.Either one or both of the code rate and the modulation may vary withinthe symbol block as frequently as on a symbol by symbol basis.

Thereafter, the method continues by performing initial estimating of thesymbols. The method then continues by performing check node updating.Thereafter, the method continues by performing symbol sequenceestimating and symbol node updating. After the iterative decodingprocessing is completed, then the method finishes by outputting bestestimates of the symbols of the received symbol block.

FIG. 28B is a flowchart illustrating an embodiment of a hybrid decodingmethod of LDPC coded modulation signals according to the invention. Thishybrid method of decoding involves updating the check nodes using thebit edge message and also updating the symbol nodes using the symbolmetric and combined bit edge message.

Many portions of this method may also include similar operational stepsof the symbol decoding method described above. For example, the methodmay also involve receiving a symbol block that includes a plurality ofsymbols. This symbol block may be viewed as being a block of LDPC codedmodulation symbols. The symbols are then mapped according to anappropriate code rate and/or modulation. The modulation includes aconstellation and a mapping for each symbol within the symbol block.Either one or both of the code rate and the modulation may vary withinthe symbol block as frequently as on a symbol by symbol basis.

This hybrid decoding method then involves obtaining soft symbolestimates from the symbol node updating. The method then involvesdecomposing the soft symbol estimates to soft bit estimates for everyedge (based on the labeling of those edges).

The method then involves estimating the bits using the soft bitestimates. The bit edge messages are then updated using the symbolmetric and the combined bit messages. The method then involves passingthese updated edge messages to the check nodes. The method then involvesupdating the edge messages at the check nodes using the bit edgemessages.

As with the symbol decoding method described above, the iterativedecoding processing is also completed within this hybrid decodingmethod. The method then finishes by outputting best estimates of thesymbols of the received symbol block.

It is also noted that the methods described within the preceding figuresmay also be performed within any of the appropriate system and/orapparatus designs (e.g., communication systems, communication devices,communication transceivers, communication receivers, and/orfunctionality described therein) that are described above withoutdeparting from the scope and spirit of the invention.

In view of the above detailed description of the invention andassociated drawings, other modifications and variations will now becomeapparent. It should also be apparent that such other modifications andvariations may be effected without departing from the spirit and scopeof the invention.

1. A decoder that is operable to decode an LDPC (Low Density ParityCheck) coded signal, the decoder comprising: a symbol sequence estimateand symbol node update block that is operable to employ an updated edgemessage to make an estimate of a symbol within the LDPC coded signal;and wherein: the edge message corresponds to an edge that connects acheck node and a symbol node within an LDPC coded modulation bipartitegraph.
 2. The decoder of claim 1, further comprising: a check nodeupdate block that is operable to generate the updated edge messagecorresponding to the edge that connects the check node and the symbolnode within the LDPC coded modulation bipartite graph.
 3. The decoder ofclaim 1, further comprising: a check node update block that is operableto update the edge message corresponding to the edge that connects thecheck node and the symbol node within the LDPC coded modulationbipartite graph; and wherein: the check node update block is operable toemploy min* (min-star) processing to generate the updated edge message.4. The decoder of claim 1, further comprising: a check node update blockthat is operable to calculate a plurality of forward metrics and aplurality of backward metrics that correspond to the symbol within theLDPC coded signal; and wherein: the check node update block that isoperable to use the plurality of forward metrics and the plurality ofbackward metrics to update the edge message corresponding to the edgethat connects the check node and the symbol node within the LDPC codedmodulation bipartite graph.
 5. The decoder of claim 1, wherein: thesymbol node corresponds to a plurality of bits within the LDPC codedsignal.
 6. The decoder of claim 1, wherein: the symbol within the LDPCcoded signal is a first symbol within the LDPC coded signal; the firstsymbol within the LDPC coded signal includes a first plurality of bits;and the second symbol within the LDPC coded signal includes a secondplurality of bits.
 7. The decoder of claim 1, wherein: the symbol withinthe LDPC coded signal is a first symbol within the LDPC coded signal;the first symbol within the LDPC coded signal is mapped to a firstconstellation whose constellation points are mapped according to a firstmapping; and a second symbol within the LDPC coded signal is mapped to asecond constellation whose constellation points are mapped according toa second mapping.
 8. The decoder of claim 1, wherein: the symbol withinthe LDPC coded signal is a first symbol within the LDPC coded signal;the first symbol within the LDPC coded signal is mapped to aconstellation when its constellation points are mapped according to afirst mapping; and a second symbol within the LDPC coded signal ismapped to the constellation when its constellation points are mappedaccording to a second mapping.
 9. The decoder of claim 1, wherein: thesymbol within the LDPC coded signal is a first symbol within the LDPCcoded signal; the first symbol within the LDPC coded signal has a firstcode rate; and a second first symbol within the LDPC coded signal has asecond code rate.
 10. The decoder of claim 1, wherein: the decoder isimplemented within a communication device; and the communication deviceis implemented within at least one of a satellite communication system,an HDTV (High Definition Television) communication system, a cellularcommunication system, a microwave communication system, a point-to-pointcommunication system, a uni-directional communication system, abi-directional communication system, a one to many communication system,a fiber-optic communication system, a WLAN (Wireless Local Area Network)communication system, and a DSL (Digital Subscriber Line) communicationsystem.
 11. A decoder that is operable to decode an LDPC (Low DensityParity Check) coded signal, the decoder comprising: a check node updateblock that is operable to update an edge message corresponding to anedge that connects a check node and a symbol node within an LDPC codedmodulation bipartite graph using min* (min-star) processing; and asymbol sequence estimate and symbol node update block that is operableto: receive the updated edge message from the check node update block;and employ the updated edge message to make an estimate of a symbolwithin the LDPC coded signal.
 12. The decoder of claim 11, wherein: thesymbol within the LDPC coded signal is a first symbol within the LDPCcoded signal; the first symbol within the LDPC coded signal includes afirst plurality of bits; and the second symbol within the LDPC codedsignal includes a second plurality of bits.
 13. The decoder of claim 11,wherein: the symbol within the LDPC coded signal is a first symbolwithin the LDPC coded signal; the first symbol within the LDPC codedsignal is mapped to a first constellation whose constellation points aremapped according to a first mapping; and a second symbol within the LDPCcoded signal is mapped to a second constellation whose constellationpoints are mapped according to a second mapping.
 14. The decoder ofclaim 11, wherein: the symbol within the LDPC coded signal is a firstsymbol within the LDPC coded signal; the first symbol within the LDPCcoded signal is mapped to a constellation when its constellation pointsare mapped according to a first mapping; and a second symbol within theLDPC coded signal is mapped to the constellation when its constellationpoints are mapped according to a second mapping.
 15. The decoder ofclaim 11, wherein: the symbol within the LDPC coded signal is a firstsymbol within the LDPC coded signal; the first symbol within the LDPCcoded signal has a first code rate; and a second first symbol within theLDPC coded signal has a second code rate.
 16. The decoder of claim 11,wherein: the decoder is implemented within a communication device; andthe communication device is implemented within at least one of asatellite communication system, an HDTV (High Definition Television)communication system, a cellular communication system, a microwavecommunication system, a point-to-point communication system, auni-directional communication system, a bi-directional communicationsystem, a one to many communication system, a fiber-optic communicationsystem, a WLAN (Wireless Local Area Network) communication system, and aDSL (Digital Subscriber Line) communication system.
 17. A method fordecoding an LDPC (Low Density Parity Check) coded signal, the methodcomprising: receiving an updated edge message that corresponds to anedge that connects a check node and a symbol node within an LDPC codedmodulation bipartite graph; and employing the updated edge message tomake an estimate of a symbol within the LDPC coded signal.
 18. Themethod of claim 17, further comprising: generating the updated edgemessage that corresponds to the edge that connects the check node andthe symbol node within the LDPC coded modulation bipartite graph usingmin* (min-star) processing.
 19. The method of claim 17, wherein: thesymbol within the LDPC coded signal is a first symbol within the LDPCcoded signal; the first symbol within the LDPC coded signal is mapped toa first constellation whose constellation points are mapped according toa first mapping; and a second symbol within the LDPC coded signal ismapped to a second constellation whose constellation points are mappedaccording to a second mapping.
 20. The method of claim 17, wherein: thesymbol within the LDPC coded signal is a first symbol within the LDPCcoded signal; the first symbol within the LDPC coded signal has a firstcode rate; and a second first symbol within the LDPC coded signal has asecond code rate.